speculative_spin_rw_mutex Class (Community Preview Feature)

speculative_spin_rw_mutex Class (Community Preview Feature)

Summary

Class that models ReaderWriterMutex Concept, and for processors which support hardware transactional memory (such as Intel® Transactional Synchronization Extensions (Intel® TSX)) may be implemented in a way that allows non-contending changes to the protected data to proceed in parallel.

The speculative_spin_rw_mutex is a Community Preview Feature that requires linkage with the Community Preview shared library.

Syntax

class speculative_spin_rw_mutex;

Header

#define TBB_PREVIEW_SPECULATIVE_SPIN_RW_MUTEX
#include "tbb/spin_rw_mutex.h"
            

Description

A speculative_spin_rw_mutex models the ReaderWriterMutex Concept. It is not scalable, fair or recursive. A speculative_spin_rw_mutex is like a spin_rw_mutex, but may provide better throughput than non-speculative mutexes when

Otherwise it performs like a spin_rw_mutex, possibly with worse throughput.

Please see the Speculative locking section for more details.

Caution

The speculative_spin_rw_mutex is padded to ensure each instance appears on a separate cache line not shared with any other data. Because of that the size of the mutex is three times the cache line size.

Caution

For the implementation of speculative_spin_rw_mutex in Intel® Threading Building Blocks (Intel® TBB)) version 4.2 running on a 4th generation Intel® Core™ processor, any lock nesting may thwart speculation.

Caution

Depending on the version of Intel TBB and the hardware, other caveats may apply. Please check the Release Notes for more information.

References

Intel® 64 and IA-32 Architectures Optimization Reference Manual, Order Number 248966-027, June 2013 , Chapter 12.

Members

See ReaderWriterMutex Concept.

See Also