speculative_spin_mutex Class

speculative_spin_mutex Class

Summary

Class that models Mutex Concept using a spin lock, and for processors which support hardware transactional memory (such as Intel® Transactional Synchronization Extensions (Intel® TSX)) may be implemented in a way that allows non-contending changes to the protected data to proceed in parallel.

Syntax

class speculative_spin_mutex;

Header

#include "tbb/spin_mutex.h"

Description

A speculative_spin_mutex models the Mutex Concept. It is not fair and not recursive. A speculative_spin_mutex is like a spin_mutex, but may provide better throughput than non-speculative mutexes when

Otherwise it performs like a spin_mutex, possibly with worse throughput.

Please see the Speculative locking section for more details.

Caution

The speculative_spin_mutex is padded to ensure each instance appears on a separate cache line not shared with any other data. Because of that the size of the mutex is twice the cache line size.

Caution

For the implementation of speculative_spin_mutex in Intel® Threading Building Blocks (Intel® TBB)) version 4.2 running on a 4th generation Intel® Core™ processor, any lock nesting may thwart speculation.

Caution

Depending on the version of Intel TBB and the hardware, other caveats may apply. Please check the Release Notes for more information.

References

Intel® 64 and IA-32 Architectures Optimization Reference Manual, Order Number 248966-027, June 2013 , Chapter 12.

Members

See Mutex Concept.

See Also